Do You Have a Challenge?
This page is dedicated to challenges in advanced silicon designs. Whether you need to reduce design cycle time or improve quality, we are interested in knowing about your challenges.
Please help us, help you.
Do You Have a Simulation Challenge?
We are focused on solving simulation problems using methodology, tools, and innovation.
We need your help to identify a schematic or post-layout simulation challenge. Whether it’s because of design size, too many parasitics at newer nodes, or too many corners.
Let us know by email (Simulation Challenge). Mutual NDA is not a problem.
Do You Have a Synthesis Challenge?
We are focused on solving RTL synthesis problems using methodology and tools.
We need your help to identify an RTL synthesis challenge. Whether it’s because of design size, too many interconnects, timing problems, routability, or run times.
Let us know by email (Synthesis Challenge). Mutual NDA is not a problem.
Do You Have a Flip-Chip Challenge?
We have gone through most of these challenges in bottom-up, top-down, and combination approaches. We are committed to simplifying chip-to-package synchronization, bump inventory maintenance, bump routability, and bump route quality analysis. There are methodology solutions and automation that could help.
We need your help to identify any flip-chip or packaging challenge that’s becoming a hurdle in producing successful chips.
Let us know by email (Flip Chip Challenge). Mutual NDA is not a problem.
Do You Have an Advanced Node Challenge?
We are focused on solving problems specific to advanced nodes. Our special interest is in geometries 65nm and below. We have methodology and guidance to address most issues.
We need your help to identify any specific challenge you are facing on advanced technology nodes. Whether it’s because of a large number of parasitics, yield, or on-chip variations.
Let us know by email (Technology Challenge). Mutual NDA is not a problem.
Do You Have a Design Cycle Challenge?
We are focused on solving various design cycle timeline-related challenges with the use of methodology, automation, rules, and data management.
We need your help to identify any problem that generally makes you slip your schedule.
We believe design architecture is the core of semiconductor companies. We are interested in any challenges other than design architecture that make it difficult to meet deadlines. Whether it’s because of lack of time, lack of expertise, number of tasks, size of design, or verification challenges.
Let us know by email (Design Cycle Challenge). Mutual NDA is not a problem.